Towards steep slope MOSFETs using ferroelectric negative capacitance

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  2. Professor Anthony O'Neill
  3. Dan Appleby
  4. Dr Nilhil Ponon
  5. Dr Kelvin Kwa
Author(s)O'Neill A, Appleby D, Ponon N, Kwa K
Publication type Conference Proceedings (inc. Abstract)
Conference Name12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
Conference LocationGuilin, China
Year of Conference2014
Source Publication Date
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Effective negative capacitance has been postulated in ferroelectrics because there is hysteresis in plots of polarization-electric field. In future integrated circuits, the incorporation of negative capacitance into MOSFET gate stacks would reduce the sub-threshold slope, enabling low power operation and reduced self-heating. As a step towards meeting this challenge, effective negative capacitance is demonstrated at room temperature in metal-insulator-metal capacitors, where it is stabilized by the presence of a paraelectric material.
NotesInvited paper at ICSICT 2014, Guilin, China
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