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Towards steep slope MOSFETs using ferroelectric negative capacitance

Lookup NU author(s): Professor Anthony O'Neill, Dan Appleby, Dr Nilhil Ponon, Dr Kelvin Kwa

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Abstract

Effective negative capacitance has been postulated in ferroelectrics because there is hysteresis in plots of polarization-electric field. In future integrated circuits, the incorporation of negative capacitance into MOSFET gate stacks would reduce the sub-threshold slope, enabling low power operation and reduced self-heating. As a step towards meeting this challenge, effective negative capacitance is demonstrated at room temperature in metal-insulator-metal capacitors, where it is stabilized by the presence of a paraelectric material.

Publication metadata

Author(s): O'Neill A, Appleby D, Ponon N, Kwa K

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Year of Conference: 2014

Pages: 1-4

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ICSICT.2014.7021281

DOI: 10.1109/ICSICT.2014.7021281

Notes: Invited paper at ICSICT 2014, Guilin, China

Library holdings: Search Newcastle University Library for this item

ISBN: 9781479932962

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