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Virtual self-timed blocks for systems-on-chip

Lookup NU author(s): Dr Fei Xia, Professor Alex Yakovlev


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Intellectual Properties (IP cores) are widely used as pre-designed and reusable units in various System-On-Chip (SOC) designs, but their integration has presented difficulties for system designers. In this paper, we propose an approach to better reuse IP cores while maintain energy efficiency for SOC systems. Here we employ a so called Self-Timed Event Processor (STEP) to, make each IP core into a virtual self-timed block. Much of the IP cores' pre-designed properties can be preserved and the new SOC systems that use virtual self-timed blocks can be more energy efficient. A MATLAB based investigation is carried out on an example STEP processor.

Publication metadata

Author(s): Chen Y, Xia F, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Unknown

Conference Name: 2006 IEEE International Symposium on Circuits and Systems. ISCAS 2006

Year of Conference: 2006

Pages: 1969-1972

Publisher: IEEE


DOI: 10.1109/ISCAS.2006.1692998

Library holdings: Search Newcastle University Library for this item

ISBN: 0780393899