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Wave-pipeliend intra-chip signalling for on-FPGA communications

Lookup NU author(s): Dr Terrence Mak

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Abstract

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.

Publication metadata

Author(s): Mak T, Sedcole P, Cheung P, Luk W

Publication type: Article

Publication status: Published

Journal: Integration, the VLSI Journal

Year: 2010

Volume: 43

Issue: 2

Pages: 188-201

Print publication date: 29/01/2010

ISSN (print): 0167-9260

ISSN (electronic): 1872-7522

Publisher: Elsevier BV

URL: http://dx.doi.org/10.1016/j.vlsi.2010.01.002

DOI: 10.1016/j.vlsi.2010.01.002

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