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Asynchronous FPGA Architecture with Distributed Control

Lookup NU author(s): Dr Delong Shang, Dr Fei Xia, Professor Alex Yakovlev


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Asynchronous techniques have become more significant with continued scaling of VLSI technologies. This paper proposes an asynchronous FPGA architecture. Different from previous methods of introducing asynchrony into FPGAs, our method seeks to preserve the current FPGA cell structure as much as possible, whilst achieving delay insensitivity in the inter-cell interconnects. By using David Cells as the central technique in the delay insensitive clock replacement, this method is conducive to the establishment of an automatic design and synthesis flow. It also particularly caters for low power designs, where current FPGA solutions are not effective yet.

Publication metadata

Author(s): Shang D, Xia F, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2010 IEEE International Symposium on Circuits and Systems

Year of Conference: 2010

Pages: 1436-1439

Publisher: IEEE


DOI: 10.1109/ISCAS.2010.5537316

Library holdings: Search Newcastle University Library for this item

ISBN: 9781424453085