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Lookup NU author(s): Professor Paul Watson
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This paper discusses the problems of implementing a parallel machine architecture to support graph reduction. In particular it examines the area of memory organization and the mechanisms which are required to ensure that the full benefits of this implementation strategy are maintained whilst achieving an efficient physical structure. The major areas of interest are the maintenance of locality and the use of storage management techniques which minimize communication.
Author(s): Watson I, Watson P
Editor(s): Fasel, J.H., Keller, R.M.
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Graph Reduction Workshop
Year of Conference: 1987
ISSN: 0302-9743 (Print) 1611-3349 (Online)
Library holdings: Search Newcastle University Library for this item
Series Title: Lecture Notes in Computer Science