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An Advanced VLSI Security Device Employing Data Verification Features

Lookup NU author(s): Professor Satnam Dlay, Dr Albert Koelmans, Martin McLauchlan, Professor David Kinniment

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Abstract

A fast CMOS VLSI device is describted which, with the use of flexible programmable on-chip control and external control lines, provides the capability to execute the Data Encryption Standard (DES)[2,3,4] algorithm. The device is known as the VERIFIED INPUT SECURITY DEVICE (VISD) since it enables transmitted and received data to be verified by the use of parity checking. The device is directly compatible with most microprocessor families, to which it appears as an 8-byte static RAM, and it is also directly compatible with msot DMA controllers, to which it appears like most peripheral devices. The device uses two clocks, a FAST CLOCK for processing the DES algorithm, and a DATA CLOCK for communicating between the VISD and the MPU or system memory. Full or partial parallelism can be used between encryption and inputJoutput communication, the amount of which depends on the ratio of the DATA CLOCK to the FAST CLOCK. The data throughput rate is estimated to be up to 8Mb/s.


Publication metadata

Author(s): Iliev VI, Dlay SS, Koelmans AM, McLauchlan MR, Kinniment DJ

Publication type: Report

Publication status: Published

Series Title: Computing Laboratory Technical Report Series

Year: 1988

Pages: 34

Print publication date: 01/10/1988

Source Publication Date: October 1988

Report Number: 271

Institution: Computing Laboratory, University of Newcastle upon Tyne

Place Published: Newcastle upon Tyne

URL: http://www.cs.ncl.ac.uk/publications/trs/papers/271.pdf


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