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Modelling and Verification of Timing Conditions with the Boyer-Moore Prover

Lookup NU author(s): Dr Albert Koelmans, Professor David Kinniment



Timing verification of digital systems can be performed by the use of formal transformations of the system structure as expressed in a hardware description language, using a standard theorem prover such as Boyer Moore. By modelling waveforms and associated timing functions in the Boyer Moore logic, it is possible to prove very general theorems about timing properties of combinatorial and feedback systems.

Publication metadata

Author(s): Koelmans AM, Kinniment DJ

Publication type: Report

Publication status: Published

Series Title: Computing Laboratory Technical Report Series

Year: 1991

Pages: 16

Print publication date: 01/10/1991

Source Publication Date: October 1991

Report Number: 346

Institution: Computing Laboratory, University of Newcastle upon Tyne

Place Published: Newcastle upon Tyne