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High Level Modelling and Design of Asynchronous Interface Logic

Lookup NU author(s): Professor Alex Yakovlev, Dr Albert Koelmans



Asynchronous digital interface circuits exhibit a high degree of concurrency. Self-timed implementation is the most appropriate design discipline for such circuits. Their complexity demands that a formal design methodology, amenable to automation, is used to design them. Existing specification models suffer from severe limitations when it comes to describing the circuit function at a high level, which requires decomposing the specification into intercommunicating sub-modules and synthesizing a logic circuit implementation of that function. We propose a new methodology to design asynchronous circuits that is divided in two stages: abstract synthesis and logic synthesis. The first stage is carried out by refining an abstract model, based on logic predicates describing the correct input-output behaviour of the circuit, into a labelled Petri net and then into a formalization of timing diagrams (the Signal Transition Graph). This refinement involves hierarchical decomposition of the initial implementation until its size can be handled by automated logic synthesis tools, as well as replacing symbolic events occurring on the input-output ports of the labelled Petri net with up and down transitions occurring on the input-output wires of a circuit implementation.

Publication metadata

Author(s): Yakovlev A, Koelmans AM, Lavagno L

Publication type: Report

Publication status: Published

Series Title: Department of Computing Science Technical Report Series

Year: 1993

Pages: 41

Print publication date: 01/01/1993

Source Publication Date: 1993

Report Number: 460

Institution: Department of Computing Science, University of Newcastle upon Tyne

Place Published: Newcastle upon Tyne