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Lookup NU author(s): Dr Victor Khomenko, Professor Maciej KoutnyORCiD, Professor Alex Yakovlev
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs. In this paper, we avoid constructing the reachability graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. We propose an efficient algorithm for logic synthesis based on the Incremental Boolean Satisfiability (SAT) approach. Following the description of our method, we present some problem-specific optimization rules. Experimental results show that this technique leads not only to huge memory savings when compared with the methods based on reachability graphs, but also to significant speedups in many cases.
Author(s): Khomenko V, Koutny M, Yakovlev A
Publication type: Report
Publication status: Published
Series Title: School of Computing Science Technical Report Series
Year: 2003
Pages: 19
Print publication date: 01/08/2003
Source Publication Date: August 2003
Report Number: 813
Institution: School of Computing Science, University of Newcastle upon Tyne
Place Published: Newcastle upon Tyne
URL: http://www.cs.ncl.ac.uk/publications/trs/papers/813.pdf
