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Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design

Lookup NU author(s): Dr Andrey Mokhov, Arseniy Alekseyev, Professor Alex Yakovlev


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There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the Conditional Partial Order Graph (CPOG) model introduced recently, which is a formalism for efficient specification and synthesis of microcontrol circuits. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. This paper presents a method for optimal encoding of a given set of partial orders so that a CPOG containing all of them has the minimum complexity, thereby leading to the smallest and fastest controller.

Publication metadata

Author(s): Mokhov A, Alekseyev A, Yakovlev A

Editor(s): Gomes, L., Khomenko, V., Fernandes, J.M.

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 10th International Conference on Application of Concurrency to System Design (ACSD)

Year of Conference: 2010

Pages: 3-12

ISSN: 1550-4808

Publisher: IEEE Computer Society


DOI: 10.1109/ACSD.2010.30

Library holdings: Search Newcastle University Library for this item

ISBN: 9781424472666