Browse by author
Lookup NU author(s): Crescenco D'Alessandro,
Dr Alex Bystrov,
Professor Alex Yakovlev
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
We report the results of the first prototype chip containing a silicon implementation of dual-rail phase-encoded links, where information is transmitted using the order of events on a pair of wires. The results show successful communication at bitrates exceeding 2 GB/s using standard-cell implementations on a 0.13μm technology. © 2008 IEEE.
Author(s): D'Alessandro C, Bystrov A, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 34th European Solid-State Circuits Conference (ESSCIRC 2008)
Year of Conference: 2008
Library holdings: Search Newcastle University Library for this item