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Logic Decomposition of Asynchronous Circuits Using STG Unfoldings

Lookup NU author(s): Dr Victor Khomenko

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Abstract

A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilisation and highly optimised circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory consumption and runtime.


Publication metadata

Author(s): Khomenko V

Editor(s): Bainbridge, J., Jones, I.

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Year of Conference: 2011

Pages: 3-12

ISSN: 1522-8681

Publisher: IEEE

URL: http://dx.doi.org/10.1109/ASYNC.2011.10

DOI: 10.1109/ASYNC.2011.10

Library holdings: Search Newcastle University Library for this item

Series Editor(s): 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

ISBN: 9781612849737


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