Browse by author
Lookup NU author(s): Dr Terrence Mak
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
Recent technological advance in three-dimensional (3-D) on-chip systems integration provides a promising platform to realize multicore, multiprocessor, and networks-on-chip (NoC) based systems with augmented performance. With the additional tightly coupled physical layers, on-chip system complexity grows significantly. The provision for efficient run-time management in large-scale system becomes critical. In this article, we review the design of an emerging on-chip dynamic-programming (DP) network, of which the capabilities have been demonstrated in a range of applications including optimal paths planning, dynamic routing and deadlock detection. A design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3-D) architecture using through-silicon-via (TSV) CMOS technology, is also presented. The vertical inter-layer communication is achieved by the means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. Testing results demonstrated the effectiveness of such approach for deadlock detection and the minuscule computational delay for detecting deadlock from a large-scale network.
Author(s): Mak T, Al-Dujaily R, Zhou K, Lam K, Poon C
Publication type: Article
Publication status: Published
Journal: IEEE Circuits and Systems Magazine
Print publication date: 22/08/2011
ISSN (print): 1531-636X
ISSN (electronic): 1558-0830
Altmetrics provided by Altmetric