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Variation Tolerant Asynchronous FPGA

Lookup NU author(s): Hock LOW, Dr Delong Shang, Dr Fei Xia, Professor Alex Yakovlev


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This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets power supply variations, including modes such as dynamic voltage scaling and variable Vdd, such as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

Publication metadata

Author(s): Low HS, Shang DL, Xia F, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 17th International Symposium on Asynchronous Circuits and Systems (ASYNC)

Year of Conference: 2011

Pages: 77-86

ISSN: 9781612849737

Publisher: Institution of Electronic and Electrical Engineers


DOI: 10.1109/ASYNC.2011.17

Library holdings: Search Newcastle University Library for this item