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Encoding of processor instruction sets with explicit concurrency control

Lookup NU author(s): Dr Andrey Mokhov, Arseniy Alekseyev, Professor Alex Yakovlev


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There is a critical need for design automation in microarchitectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a set of formal methods and a software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the conditional partial order graph (CPOG) model, which is a formalism for efficient specification and synthesis of microcontrollers. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. The paper shows that the CPOG model is a very convenient formalism for efficient representation of processor instruction sets. It provides a ground for a concise formulation of several encoding problems, which are reducible to the Boolean satisfiability (SAT) problem and can be efficiently solved by modern SAT solvers.

Publication metadata

Author(s): Mokhov A, Alekseyev A, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IET Computers and Digital Techniques

Year: 2011

Volume: 5

Issue: 6

Pages: 427-439

Print publication date: 01/11/2011

ISSN (print): 1751-8601

ISSN (electronic): 1751-861X

Publisher: The Institute of Engineering and Technology


DOI: 10.1049/iet-cdt.2010.0158


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