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Lookup NU author(s): Dr Ghaith Tarawneh, Professor Alex Yakovlev
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We present a novel intra-chip physical parameter sensor that exploits the clock-to-q delay response of flip-flops. The proposed design relies on deliberately violating the setup and hold time conditions of a flip-flop to bring it into metastable states and increase its clock-to-q delay. Traditionally, this is an undesired effect because it can result in unpredictable system failures. In this work, this phenomenon is exploited to quantify variations in intra-chip physical parameters. Our design has three benefits over conventional ring-oscillator-based sensors; it consumes less device resources, has a higher precision and does not require a high clock frequency. We present a small-signal model of the proposed sensor and compare its performance with ring oscillators by conducting voltage and temperature-controlled experiments on an Altera Cyclone II FPGA device.
Author(s): Tarawneh G, Mak T, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 22nd International Conference on Field Programmable Logic and Applications (FPL)
Year of Conference: 2012
Pages: 373-379
ISSN: 9781467322553
Publisher: IEEE
URL: http://dx.doi.org/10.1109/FPL.2012.6339207
DOI: 10.1109/FPL.2012.6339207
Library holdings: Search Newcastle University Library for this item
ISBN: 9781467322577
