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Lookup NU author(s): Dr Ghaith Tarawneh, Professor Alex Yakovlev
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We show that synchronizers that operate under Dynamic Voltage Frequency Scaling exhibit exponential failure rate variations due to the disproportionate scaling of propagation delay and the parameter τ. Therefore, the optimum number of synchronization cycles for a design can vary dynamically depending on its voltage/frequency operating point. To address this problem, we present an adaptive clock domain interface that optimizes synchronization latency by evaluating flip-flop synchronization performance dynamically. The proposed design meets a reliability criterion without relying on excessively-conservative synchronizers to accommodate for worst-case performance.
Author(s): Tarawneh G, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 22nd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2012)
Year of Conference: 2012
Pages: 93-102
ISSN: 0302-9743
Publisher: Springer Berlin Heidelberg
URL: http://dx.doi.org/10.1007/978-3-642-36157-9_10
DOI: 10.1007/978-3-642-36157-9_10
Library holdings: Search Newcastle University Library for this item
ISBN: 9783642361562
