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Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

Lookup NU author(s): Dr Arfan Ghani

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Abstract

This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation.

Publication metadata

Author(s): Ghani A, See CH, Ali SMU

Publication type: Article

Publication status: Published

Journal: IET Science, Measurement and Technology

Year: 2014

Volume: 8

Issue: 6

Pages: 432-440

Print publication date: 01/11/2014

ISSN (print): 1751-8822

ISSN (electronic): 1751-8830

Publisher: INST ENGINEERING TECHNOLOGY-IET

URL: http://dx.doi.org/10.1049/iet-smt.2014.0004

DOI: 10.1049/iet-smt.2014.0004

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