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Modelling concurrency in processor instruction sets

Lookup NU author(s): Alessandro De Gennaro



This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).


Complexity of processors available in the market continuously increases, forcing designers to have more systematic approaches to plan new processor architectures. The task of finding new models to represent event-based systems (likewise processor's instructions) becomes increasingly important, pushing research to be focused on this topic. Models should be able to elegantly capture either sequential and concurrent behaviours; the latter ones are particularly important as they are the key to a high throughput. Another increasingly required feature of processor's controller is the scalability. Instruction Set Architectures (ISAs) are often updated for supporting more instructions, this requires the possibility of adding any instructions into a system to be a non-invasive process.The main topic of this work is the development of automated software tools for the formal specification, verification and synthesis of processor instruction sets, with particular focus on overcoming the challenges associated with concurrency. Due to the page limit, we only give a brief overview of the problem domain and highlight recent results in automated encoding of instructions presented at the International Conference on Application of Concurrency to System Design, ACSD'2015.

Publication metadata

Author(s): de Gennaro A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 12th LASER Summer School on Software Engineering - Concurrency: the next frontiers

Year of Conference: 2015

Online publication date: 31/08/2015

Acceptance date: 15/08/2015

Date deposited: 14/09/2015

Publisher: LASER Summer School on Software Engineering