Toggle Main Menu Toggle Search

Open Access padlockePrints

Design of a DCO based on Worst-Case Delay of a Self-Timed Counter and a Digitally controllable Delay Path

Lookup NU author(s): Oyinkuro Benafa, Austin Ogweno, Dr Delong Shang, Professor Alex Yakovlev


Full text for this publication is not currently held within this repository. Alternative links are provided below where available.


Delay path reconfiguration is used to control frequency output in Digitally Controlled Oscillators. In order to achieve a very low frequency range, if the delay path is not properly designed, this would result in large area overhead and leakage power loss. An alternative delay path is proposed for the DCO, based on a unit delay as the smallest possible delay, with added architecture to multiply the unit delay using digital control bits, this allows the delay output to be near-linear. The proposed delay path has two control modes, a 2-bits fine grain control and 6-bit coarse control. Simulation results show that the frequency of the DCO ranges from 34.92MHz to 448MHZ at 1.1V with maximum average power consumption of 358.27 mu W at 1.1V.

Publication metadata

Author(s): Benafa O, Ogweno A, Shang DL, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

Year of Conference: 2016

Online publication date: 24/10/2016

Acceptance date: 02/04/2016

Publisher: IEEE


DOI: 10.1109/NEWCAS.2016.7604821

Library holdings: Search Newcastle University Library for this item

ISBN: 9781467389013