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Static Verification of Railway Schema and Interlocking Design Data

Lookup NU author(s): Dr Alexei Iliasov, Dr Paulius Stankaitis, David Adjepon-Yamoah


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The paper presents an experience of verifying a large scale, real-life dataset describing various aspects of railway station design. We discuss how a number of assorted digital artefacts were pooled together and converted into a set-theoretic model over which a type inference procedure is run. The typed model is then used to confirm or contradict logical conjectures over data elements. We employ a number of state-of-the-art SMT solvers as a verification back-end. The project is ongoing but has already identified a number of issues in topology definition and signalling data that were missed by other automated tests and not revealed by simulation tools.

Publication metadata

Author(s): Iliasov A, Stankaitis P, Adjepon-Yamoah D

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Reliability, Safety, and Security of Railway Systems: Modelling, Analysis, Verification, and Certification (RSSRail 2016)

Year of Conference: 2016

Pages: 123-133

Online publication date: 15/06/2016

Acceptance date: 02/04/2016

ISSN: 0302-9743

Publisher: Springer


DOI: 10.1007/978-3-319-33951-1_9

Library holdings: Search Newcastle University Library for this item

Series Title: Lecture Notes in Computer Science

ISBN: 9783319339504