UIS failure mechanism of SiC power MOSFETs

Fayyaz, A; Castellazzi, A; Romano, G; Riccio, M; Irace, A; Urresti, J; Wright, N

doi:10.1109/WiPDA.2016.7799921

UIS failure mechanism of SiC power MOSFETs

Lookup NU author(s): Asad Fayyaz, Dr Jesus Urresti Ibanez ORCiD

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Abstract

This paper investigates the failure mechanism of SiC power MOSFETs during avalanche breakdown under unclamped inductive switching (UIS) test regime. Switches deployed within motor drive applications could experience undesired avalanche breakdown events. Therefore, avalanche ruggedness is an important feature of power devices enabling snubber-less converter design and is also a desired feature in certain applications such as automotive. It is essential to thoroughly characterize SiC power MOSFETs for better understanding of their robustness and more importantly of their corresponding underling physical mechanisms responsible for failure in order to inform device design and technology evolution. Experimental results during UIS at failure and 2D TCAD simulation results are presented in this study.