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Gate Stack Engineering for High Temperature Silicon Carbide CMOS ICs

Lookup NU author(s): Dr Ming-Hung Weng, Dr Hua Khee Chan, Dr Alton Horsfall


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The potential to thermally grow SiO2 on silicon carbide has resulted in it becoming the technology of choice to realise high temperature CMOS circuits. The challenge to achieve a high quality gate stack relies on engineering the metal-insulator-semiconductor interfaces to enable reliable high temperature functionality. Here we describe the effect of different process conditions for the formation of the dielectric layer on the characteristics of the resulting devices. The operating characteristics at elevated temperatures depend critically on the quality of the gate stack. Therefore a systematic evaluation of the intrinsic properties of the gate stack and data from reliability tests are needed.

Publication metadata

Author(s): Weng MH, Murphy AD, Clark DT, Smith DA, Thompson RF, Young RAR, Ramsay EP, Chan HK, Horsfall AB

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: IMAPS International Conference on High Temperature Electronics Network, HiTEN 2015

Year of Conference: 2015

Pages: 33-36

Print publication date: 01/07/2015

Acceptance date: 01/01/1900

Publisher: IMAPS-International Microelectronics and Packaging Society


DOI: 10.4071/HiTEN-Session1-Paper1_6