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Analysis of FXP adders and multipliers for speed- and area-efficient LNS arithmetic unit

Lookup NU author(s): Dr Nick Coleman


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© 2014 IEEE. This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers, each of the arithmetic is functionally verified and synthesised using Synopsys Design Compiler in Faraday 0.18 μm CMOS technology based on a 32-bit system. Two types of performance measurement, which are the worst-case delay and the silicon area, are chosen as the evaluation arguments. From conducted analytical studies, the CLA/CSLA adder and Booth recoded with Wallace tree multiplier were the best FXP adder and multiplier blocks to be applied in the system since they were the fastest designs. Using these blocks, the synthesis of the LNS system produced an approximately 7.10 ns of critical delay for addition and subtraction, and solely 1.16 ns for multiplication and division. The total area for a complete LNS architecture was 599,871 μm2, in which 65% the size of previously designed LNS architecture of ELM.

Publication metadata

Author(s): Ismail RC, Naziri SZM, Murad SAZ, Coleman JN

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2014 2nd International Conference on Electronic Design (ICED 2014)

Year of Conference: 2014

Pages: 238-243

Online publication date: 22/01/2015

Acceptance date: 01/01/1900

Publisher: IEEE


DOI: 10.1109/ICED.2014.7015806

Library holdings: Search Newcastle University Library for this item

ISBN: 9781479961030