Language and Hardware Acceleration Backend for Graph Processing

Mokhov, A; De, Gennaro, A; Tarawneh, G; Wray, J; Lukyanov, G; Mileiko, S; Scott, J; Yakovlev, A; Brown, A

doi:10.1109/FDL.2017.8303899

Language and Hardware Acceleration Backend for Graph Processing

Lookup NU author(s): Dr Andrey Mokhov, Alessandro De Gennaro, Dr Ghaith Tarawneh, Dr Sergey Mileiko, Professor Alex Yakovlev

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This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).

Abstract

Graphs are important in many applications however their analysis on conventional computerarchitectures is generally inefficient because it involves highly irregular access tomemory when traversing vertices and edges. As an example, when finding a path from a sourcevertex to a target one the performance is typically limited by the memory bottleneck whereasthe actual computation is trivial.This paper presents a methodology for embedding graphs into silicon, where graph verticesbecome finite state machines communicating via the graph edges. With this approach many commongraph analysis tasks can be performed by propagating signals through the physical graph andmeasuring signal propagation time using the on-chip clock distribution network. This eliminatesthe memory bottleneck and allows thousands of vertices to be processed in parallel.We present a domain-specific language for graph description and transformation, and demonstratehow it can be used to translate application graphs into an FPGA board, where they can beanalysed 1000x faster than on a conventional computer cluster.