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Reducing switching noise effects by advanced clock management

Lookup NU author(s): Professor Alex Yakovlev



© 2017 IEEE. In this paper an overview of different clock management methods for the reduction of switching noise is provided. On one hand, standard design-flow compliant methods such as current shaping and clock modulation can be successfully applied, especially for targeting higher harmonics of the switching noise. On the other hand, methods deploying globally-asynchronous locally-synchronous (GALS) circuits can result in very effective noise reduction of lower harmonics. With this approach it can be shown that, when a power-balanced GALS partitioning scheme is used, the switching noise reduction at lower harmonics of the clock frequency corresponds to 20logM, where M is the number of GALS partitions. A complex gigabit OFDM DSP processor, named the Moonrake chip demonstrates switching noise reduction of over 20 dB using a pausible clocking GALS architecture. The Lighthouse chip, integrating a mixed-signal 120 GHz Radar transceiver, demonstrates the potential for reducing the substrate noise. Finally, the Screamer chip, performing the function of a trusted sensor node, shows that current shaping techniques based on synchronous circuits can be successfully utilized for switching noise reduction, achieving more than 10 dB improvement in the target frequency range.

Publication metadata

Author(s): Krstic M, Fan X, Babic M, Grass E, Bjerregaard T, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Proceedings of the 2017 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMCCompo 2017)

Year of Conference: 2017

Pages: 3-8

Online publication date: 03/08/2017

Acceptance date: 02/06/2016

Date deposited: 06/11/2017

Publisher: IEEE


DOI: 10.1109/EMCCompo.2017.7998072

Library holdings: Search Newcastle University Library for this item

ISBN: 9781538626894