A low power flash-FPGA based brain implant micro-system of PID control

Xia, L; Fattah, N; Soltan, A; Jackson, A; Chester, G; Degenaar, P

doi:10.1109/EMBC.2017.8036790

A low power flash-FPGA based brain implant micro-system of PID control

Lookup NU author(s): Lijuan Xia, Sam Fattah, Dr Ahmed Abd El-Aal, Professor Andrew Jackson, Dr Graeme Chester, Professor Patrick Degenaar

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Abstract

© 2017 IEEE. In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52μJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.