Design-time reliability evaluation for digital circuits

Abufalgha, MA; Bystrov, A

doi:10.1109/IOLTS.2017.8046196

Design-time reliability evaluation for digital circuits

Lookup NU author(s): Mohamed Abufalgha, Dr Alex Bystrov

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This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2017.

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Abstract

© 2017 IEEE. A new method of evaluating the reliability of combinational circuits is proposed, this method uses two levels of characterisation: a Stochastic Fault Model (SFM) of the component library and a design-specific Critical Vector Model (CVM). The idea is to move the high-complexity problem of stochastic characterisation of parameters into the generic part of the design process, and do it just once for a great number of the specific designs. The SFM captures variations of the vector of parameters of a library component fault model, those causing a transient fault at the component output; it is meant to be supplied by the foundry, similar to timing library files. The CVM is derived by a limited number of simulation runs on the specific design, and represents the boundary between the erroneous and error-free operation, w.r.t. the vector of parameters of each component. The probability of error-free operation is subsequently calculated by jointly using SFM and CVM. The method is demonstrated on a chain of inverters for simplicity, and subsequently applied to a 3-bit full adder. A complex three-way trade-off between energy, performance and reliability is explored. The method is meant to serve as a basis for design-time reliability evaluation and runtime power-reliability management. A slow stage is added to the circuit under test to improve its reliability.