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Practical Verification of Railway Signalling Programs

Lookup NU author(s): Dr Alexei Iliasov, Dr Linas Laibinis, Professor Alexander RomanovskyORCiD



This is the authors' accepted manuscript of an article that has been published in its final definitive form by IEEE, 2023.

For re-use rights please refer to the publisher's terms and conditions.


SafeCap is a modern toolkit for modelling, simulation and formal verification of railway networks. This paperdiscusses the use of SafeCap for formal analysis and fully automated scalable safety verification of solid state interlocking(SSI) programs – a technology at the heart of many railway signalling solutions around the world. The main driving forcebehind SafeCap development was to make it easy for signalling engineers to use the technology and thus to ensure its smooth industrial deployment. The unique qualities and the novelty of SafeCap are in making the use of formal notations and proofs fully transparent for the engineers. In this paper we explain the formal foundations of the proposed method, its tool support, and their successful application by railway companies in developing industrial signalling projects.

Publication metadata

Author(s): Iliasov A, Taylor D, Laibinis L, Romanovsky A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Dependable and Secure Computing

Year: 2023

Volume: 20

Issue: 1

Pages: 695-707

Print publication date: 01/01/2023

Online publication date: 10/01/2022

Acceptance date: 03/01/2022

Date deposited: 30/07/2021

ISSN (print): 1545-5971

ISSN (electronic): 1941-0018

Publisher: IEEE


DOI: 10.1109/TDSC.2022.3141555

ePrints DOI: 10.57711/s50m-py51


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