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Lookup NU author(s): Venkateshwarlu Gudur, Dr Sidharth Maheshwari, Dr Rishad Shafik
This is the authors' accepted manuscript of an article that has been published in its final definitive form by IEEE, 2022.
For re-use rights please refer to the publisher's terms and conditions.
In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8 energy reduction and up to 13.3 less resource utilization when compared with the state-of-the-art software and hardware approaches.
Author(s): Gudur VY, Maheshwari S, Acharyya A, Shafik R
Publication type: Article
Publication status: Published
Journal: IEEE/ACM Transactions on Computational Biology and Bioinformatics
Year: 2022
Volume: 19
Issue: 5
Pages: 2697-2711
Print publication date: 01/09/2022
Online publication date: 20/08/2021
Acceptance date: 17/08/2021
Date deposited: 24/09/2021
ISSN (print): 1545-5963
ISSN (electronic): 1557-9964
Publisher: IEEE
URL: https://doi.org/10.1109/TCBB.2021.3106311
DOI: 10.1109/TCBB.2021.3106311
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