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Lookup NU author(s): Dr Ashur Rafiev,
Professor Alex Yakovlev,
Dr Ghaith Tarawneh
This work is licensed under a Creative Commons Attribution 4.0 International License (CC BY 4.0).
One of the key problems in designing and implementing graph analysis algorithms for distributed platforms is to find an optimal way of managing communication flows in the massively parallel processing network. Message‐passing and global synchronization are powerful abstractions in this regard, especially when used in combination. This paper studies the use of a hardware‐implemented refutable global barrier as a design optimization technique aimed at unifying these abstractions at the API level. The paper explores the trade‐offs between the related overheads and performance factors on a message‐ passing prototype machine with 49,152 RISC‐V threads distributed over 48 FPGAs (called the Partially Ordered Event‐Triggered Systems platform). Our experiments show that some graph applications favour synchronized communication, but the effect is hard to predict in general because of the interplay between multiple hardware and software factors. A classifier model is therefore proposed and implemented to perform such a prediction based on the application graph topology parameters: graph diameter, degree of connectivity, and reconvergence metric. The presented experimental results demonstrate that the correct choice of communication mode, granted by the new model‐driven approach, helps to achieve 3.22 times faster computation time on average compared to the baseline platform operation.
Author(s): Rafiev A, Yakovlev A, Tarawneh G, Naylor MN, Moore SW, Thomas DB, Bragg GM, Vousden ML, Brown AD
Publication type: Article
Publication status: Published
Journal: IET Computers & Digital Techniques
Print publication date: 01/03/2022
Online publication date: 03/04/2022
Acceptance date: 21/03/2022
Date deposited: 04/04/2022
ISSN (print): 1751-8601
ISSN (electronic): 1751-861X
Publisher: John Wiley & Sons, Inc.
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