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A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits

Lookup NU author(s): Jordan Morris, Professor Alex Yakovlev

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This work is licensed under a Creative Commons Attribution 4.0 International License (CC BY 4.0).

Abstract

This work presents complex circuitry from subthreshold standard cell libraries created by geometric STI spacer patterning for bulk planar CMOS technology nodes. Performance/leakage granularity enhancement affords safer multi-Vt synthesis in aggressive voltage scaling schemes. Libraries are evaluated in silicon through implementation of 32-bit datapath 128-bit AES cores. Intra-die nominal temperature (20 °C) analysis reveals improvements of up to 8.65×/24% MEP-to-MEP in frequency and energy-per-cycle respectively, compared to a state-of-the-art subthreshold library. A negative temperature correlation with performance enhancement is demonstrated extending beyond the cell level and into more complex designs. MEP-to-MEP performance enhancement and energy-per-cycle reduction are demonstrated over a temperature range of 0 °C to 85 °C

Publication metadata

Author(s): Morris J, Prabhat P, Myers J, Yakovlev A

Publication type: Article

Publication status: Published

Journal: Journal of Low Power Electronics and Applications

Year: 2022

Volume: 12

Issue: 3

Print publication date: 02/08/2022

Online publication date: 02/08/2022

Acceptance date: 09/07/2022

Date deposited: 02/08/2022

ISSN (electronic): 2079-9268

Publisher: MDPI

URL: https://doi.org/10.3390/jlpea12030043

DOI: 10.3390/jlpea12030043

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