Browse by author
Lookup NU author(s): Dr Fei Xia
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License (CC BY-NC-ND).
© 2013 IEEE.This paper presents a high-performance and synthesizable asynchronous pipeline (HPSAP). First, a 4-phase pipeline controlled by the relative-timing (RT) controller is designed. The controller is small (7 gates) and its handshake protocol is highly concurrent, resulting in fewer component delays in cycle time. However, the RT pipeline's throughput is limited by the inherent reset phase in the 4-phase protocol. Thus, the variant HPSAP pipeline is proposed with the quasi-2phase conversion method. Unlike other existing solutions which aimed at reducing the reset time of the 4-phase protocol, this method imitates the behavior of the 2-phase pipeline and re-activates the reset edge by two steps: 1) replacing all delay-matched units with the maximum delay; 2) adding a small pulse generator on each RT controller. The post-layout HSPICE simulation of a 4-bit 10-stage HPSAP first-in-first-out (FIFO) pipeline indicated a throughput of 5.382 giga data item per second (GDI/s) under SMIC 55nm CMOS technology, which was 77.5% and 14.65% higher than the Click pipeline and Mousetrap pipeline. In the pipeline with processing, a 32× 32 bits multiplier was built, and the maximum working frequency of the HPSAP multiplier was faster than Mousetrap and the synchronous counterparts.
Author(s): Tang X, Wang J, Li Y, Hu J, Xia F, Shang D
Publication type: Article
Publication status: Published
Journal: IEEE Access
Year: 2023
Volume: 11
Pages: 119711-119721
Online publication date: 23/10/2023
Acceptance date: 18/10/2023
Date deposited: 27/11/2023
ISSN (electronic): 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
URL: https://doi.org/10.1109/ACCESS.2023.3326856
DOI: 10.1109/ACCESS.2023.3326856
Altmetrics provided by Altmetric
