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Lifetime reliability-aware digital synthesis

Lookup NU author(s): Dr Shengyu DuanORCiD

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This is the authors' accepted manuscript of an article that has been published in its final definitive form by IEEE, 2018.

For re-use rights please refer to the publisher's terms and conditions.


Publication metadata

Author(s): Duan S, Halak B, Zwolinski M

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year: 2018

Volume: 26

Issue: 11

Pages: 2205-2216

Print publication date: 01/11/2018

Online publication date: 13/08/2018

Acceptance date: 18/07/2018

Date deposited: 10/06/2025

ISSN (print): 1063-8210

ISSN (electronic): 1557-9999

Publisher: IEEE

URL: https://doi.org/10.1109/TVLSI.2018.2861820

DOI: 10.1109/TVLSI.2018.2861820


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Funding

Funder referenceFunder name
593688
Cisco Research Center

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