Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array

Ghazal, O; Mao, G; Lan, T; Ojukwu, J; Xia, F; Yakovlev, A; Shafik, R

doi:10.1109/ISCAS46773.2023.10181560

Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array

Lookup NU author(s): Omar Awf ORCiD, Gang Mao, Tian Lan, Jesse Ojukwu, Dr Fei Xia, Professor Alex Yakovlev ORCiD, Professor Rishad Shafik ORCiD

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Abstract

Tsetlin machines (TMs) are a novel machine learning paradigm based on learning automata and Boolean logic inference, with better energy-efficiency and explainability than neural networks. This work exploits non-volatile ReRAM-transistor memory arrays to perform efficient in-memory TM computing. To accommodate the large timing variability of ReRAM devices and enhance energy efficiency and speed, the control path is implemented with quasi delay-insensitive (QDI) asynchronous circuits. The design of these circuits are derived and synthesized from their signal-transition graph specifications using the Workcraft tool. The resulting circuits offer high event-driven controllability and high variation tolerance for the mixed-signal ReRAM data path. Compared to state of the art TM hardware, the new TM design uses less than 5% of the power to achieve better than4× the performance.