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Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning

Lookup NU author(s): Dr Shengyu DuanORCiD, Dr Marcos SartoriORCiD, Professor Rishad ShafikORCiD, Professor Alex YakovlevORCiD, Professor Emre Ozer

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Abstract

Population count (popcount) is a crucial operation for many low-complexity machine learning (ML) algorithms, including Tsetlin Machine (TM)-a promising new ML method, particularly well-suited for solving classification tasks. The inference mechanism in TM consists of propositional logic-based structures within each class, followed by a majority voting scheme, which makes the classification decision. In TM, the voters are the outputs of Boolean clauses. The voting mechanism comprises two operations: popcount for each class and determining the class with the maximum vote by means of an argmax operation.While TMs offer a lightweight ML alternative, their performance is often limited by the high computational cost of popcount and comparison required to produce the argmax result. In this paper, we propose an innovative approach to accelerate and optimize these operations by performing them in the time domain. Our time-domain implementation uses programmable delay lines (PDLs) and arbiters to efficiently manage these tasks through delay-based mechanisms. We also present an FPGA design flow for practical implementation of the time-domain popcount, addressing delay skew and ensuring that the behavior matches that of the model’s intended functionality. By leveraging the natural compatibility of the proposed popcount with asynchronous architectures, we demonstrate significant improvements in an asynchronous TM, including up to 38% reduction in latency, 43.1% reduction in dynamic power, and 15% savings in resource utilization, compared to synchronous TMs using adder-based popcount.


Publication metadata

Author(s): Duan S, Sartori MLL, Shafik R, Yakovlev A, Ozer E

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 2025 29th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Year of Conference: 2025

Pages: 19-27

Print publication date: 05/06/2025

Online publication date: 05/06/2025

Acceptance date: 10/03/2025

Date deposited: 08/06/2025

Publisher: IEEE

URL: https://doi.org/10.1109/ASYNC65240.2025.00012

DOI: 10.1109/ASYNC65240.2025.00012

Library holdings: Search Newcastle University Library for this item

ISBN: 9798331503109


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