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Lookup NU author(s): Yujin ZhengORCiD, Professor Rishad ShafikORCiD, Professor Alex YakovlevORCiD
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We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28⨯28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm2. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3 k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4μs which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models.
Author(s): Anders Tunheim S, Zheng Y, Jiao L, Shafik R, Yakovlev A, Granmo OC
Publication type: Article
Publication status: Published
Journal: IEEE Transactions on Circuits and Systems I: Regular Papers
Year: 2025
Pages: Epub ahead of print
Online publication date: 14/07/2025
Acceptance date: 28/06/2025
ISSN (print): 1549-8328
ISSN (electronic): 1558-0806
Publisher: IEEE
URL: https://doi.org/10.1109/TCSI.2025.3586698
DOI: 10.1109/TCSI.2025.3586698
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