Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs

Rahman, T; Mao, G; Pattison, B; Maheshwari, S; Sartori, M; Wheeldon, A; Shafik, R; Yakovlev, A

doi:10.1109/SAS65169.2025.11105163

Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs

Lookup NU author(s): Tousif Rahman, Dr Gang Mao ORCiD, Bob Pattison, Dr Sidharth Maheshwari, Dr Marcos Sartori ORCiD, Dr Adrian Wheeldon, Professor Rishad Shafik ORCiD, Professor Alex Yakovlev ORCiD

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Abstract

© 2025 IEEE. Embedded Field-Programmable Gate Arrays (eFP-GAs) enable Machine Learning (ML) hardware accelerators to meet the latency and lower power needs of IoT-sensor-based applications when compared to traditional FPGAs. However, limited logic and memory constrain compute capabilities and model size. Unlike recent FPGA approaches prioritizing throughput, this work focuses on resource efficiency and on-field re-calibration. The proposed eFPGA accelerator enables runtime changes in model size, architecture, and input data without offline resynthesis, leveraging a bitwise compressed inference architecture of the Tsetlin Machine (TM). TM computation requires only bitwise operations (and, or, not), summations, and additions, allowing the entire model to fit in on-chip block RAM. This accelerator enables runtime model tuning while using 2.5× fewer LUTs and 3.38× fewer registers than the most resource-efficient alternative, achieving up to 129× energy reduction compared to low-power microcontrollers running the same software application.