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Synthesis of Asynchronous Circuits with Predictable Latency

Lookup NU author(s): Dr Alex Bystrov, Professor Alex YakovlevORCiD

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Abstract

A new method for low-latency asynchronous circuit design uses a two-level architecture. It consists of the explicit context logic and output flip-flops. Explicit context logic computes a single context signal for each output concurrently to the environment operation. Every flip-flop generates an output from the corresponding context and trigger signals. The flip-flop latency for every transition is defined by the number of corresponding trigger transitions and can be predicted at an early stage of the design. Explicit context logic is generated by a logic synthesis tool, which produces a near logarithmic state encoding. This is especially beneficial for the designs from specifications having implicit (hidden) counters.

Publication metadata

Author(s): Bystrov A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 11th IEEE/ACM International Workshop on Logic and Synthesis (IWLS 2002)

Year of Conference: 2002

Pages: 239-243

Date deposited: 26/11/2004

Publisher: IEEE Computer Society & ACM SIGDA

URL: http://www.informatik.uni-trier.de/~ley/db/conf/iwls/iwls2002.html

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