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Lookup NU author(s): Dr Frank Burns,
Dr Delong Shang,
Dr Albert Koelmans,
Professor Alex Yakovlev
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We present a new CAD tool set for generating asynchronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits using David Cells (DCs). Finally logic optimization tools are applied to generate speed independent (SI) circuits. The speed independent circuits generated perform well compared to circuits generated by existing asynchronous tools.
Author(s): Burns F, Shang D, Koelmans A, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04)
Year of Conference: 2004
Publisher: IEEE Computer Society
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