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An asynchronous synthesis toolset using Verilog

Lookup NU author(s): Dr Frank Burns, Dr Delong Shang, Dr Albert Koelmans, Professor Alex Yakovlev

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Abstract

We present a new CAD tool set for generating asynchronous circuits from high-level Verilog level-sensitive specifications. Initially high-level Verilog descriptions are compiled and converted into a novel intermediate Petri-net format. The intermediate format is subsequently passed to optimization tools and mapping tools where it is directly mapped into asynchronous datapath and control circuits using David Cells (DCs). Finally logic optimization tools are applied to generate speed independent (SI) circuits. The speed independent circuits generated perform well compared to circuits generated by existing asynchronous tools.

Publication metadata

Author(s): Burns F, Shang D, Koelmans A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04)

Year of Conference: 2004

Pages: 724-725

ISSN: 1530-1591

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/DATE.2004.1268948

DOI: 10.1109/DATE.2004.1268948

Library holdings: Search Newcastle University Library for this item

ISBN: 07695208551

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