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Multiple carry asynchronous estimated adder

Lookup NU author(s): Esmail Ashmila, Professor Satnam Dlay, Emeritus Professor Oliver Hinton


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Addition is one of the most important operations in any digital systems or processors because the performance of processors is significantly influenced by the speed of their adders. In this paper a novel high performance adder based on the statistical approach with multiple carries for prediction is presented. A simulation for this 32-bit adder design has been performed using a 0.125 μm CMOS technology, and the simulation results shows that this new adder design can achieve dramatic speed advantages over other adders. The delay-area product comparison shows a saving of 44.2% over a ripple adder, 41% over carry select adder; with ripple adder elements, and over 26% on carry select look-ahead adders.

Publication metadata

Author(s): Ashmila EM, Dlay SS, Hinton OR

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: IASTED International Conference on Circuits, Signals, and Systems

Year of Conference: 2004

Pages: 79-84

Publisher: IASTED

Library holdings: Search Newcastle University Library for this item

ISBN: 9780889864559