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Off-line testing of Asynchronous circuits

Lookup NU author(s): Deepali Koppad, Dr Alex Bystrov, Professor Alex YakovlevORCiD

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Abstract

A new technique to test asynchronous circuits obtained by direct mapping technique from 1-safe Petri nets is proposed. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into high-level specification, a Petri net. A "pseudo clock" is used to handle hazards and activate faults which exhibit themselves only under particular arrangements. Asynchronous citcuit obtained by Direct mapping technique can be made 100% testable for stuck-at-faults by implementing testability features. An algorithm to insert testability features and generate test sequences is presented using a benchmark. © 2005 IEEE.

Publication metadata

Author(s): Koppad D, Bystrov A, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Proceedings of the IEEE International Conference on VLSI Design

Year of Conference: 2005

Pages: 730-735

Publisher: IEEE Computer Society

URL: http://dx.doi.org/10.1109/ICVD.2005.126

DOI: 10.1109/ICVD.2005.126

Library holdings: Search Newcastle University Library for this item

ISBN: 9780769522647

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