Toggle Main Menu Toggle Search

Open Access padlockePrints

Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT

Lookup NU author(s): Dr Victor Khomenko, Professor Maciej KoutnyORCiD, Professor Alex Yakovlev


Full text for this publication is not currently held within this repository. Alternative links are provided below where available.


The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs. In this paper, we avoid constructing the reachability graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. We propose an efficient algorithm for logic synthesis based on the Incremental Boolean Satisfiability (SAT) approach. Experimental results show that this technique leads not only to huge memory savings when compared with the methods based on reachability graphs, but also to significant speedups in many cases, without affecting the quality of the solution.

Publication metadata

Author(s): Khomenko V, Koutny M, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 4th International Conference on Application of Concurrency to System Design (ACSD 2004)

Year of Conference: 2004

Pages: 49-73

ISSN: 0169-2968

Publisher: Fundamenta Informaticae: IOS Press

Library holdings: Search Newcastle University Library for this item

ISBN: 18758681