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Fast parallel-prefix architectures for modulo 2n - 1 addition with a single representation of zero

Lookup NU author(s): Professor Said Boussakta

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Abstract

Novel modulo 2n - 1 addition algorithms for RNS applications are presented. The proposed algorithms depart from the traditional approach of modulo 2n - 1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures do not only offer significant speed-up in modulo 2n - 1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area x delay2 and energy x delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology. © 2007 IEEE.

Publication metadata

Author(s): Patel RA, Benaissa M, Boussakta S

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computers

Year: 2007

Volume: 56

Issue: 11

Pages: 1484-1492

Print publication date: 01/11/2007

ISSN (print): 0018-9340

ISSN (electronic): 1557-9956

Publisher: I E E E

URL: http://dx.doi.org/10.1109/TC.2007.70750

DOI: 10.1109/TC.2007.70750

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