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Novel power-delay-area-efficient approach to generic modular addition

Lookup NU author(s): Professor Said Boussakta

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Abstract

Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. They are widely used in modular multipliers and residue-to-binary converters and in implementing other residue arithmetic operations such as scaling. In this paper, a methodology for designing power-delay-area-efficient modular adders based on carry propagate addition is presented. The binary representational characteristics of the modulus are exploited to allow the sharing of hardware in a fast modular adder topology. VLSI implementation results using 0.13-μm standard-cell technology, together with a theoretical analysis, show that this approach produces adders that offer efficient tradeoffs when compared with the fastest through to the smallest generic modular adders in the literature. © 2007 IEEE.

Publication metadata

Author(s): Patel RA, Benaissa M, Powell N, Boussakta S

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Circuits and Systems I: Regular Papers

Year: 2007

Volume: 54

Issue: 6

Pages: 1279-1292

Print publication date: 01/06/2007

ISSN (print): 1549-8328

ISSN (electronic): 1558-0806

Publisher: IEEE

URL: http://dx.doi.org/10.1109/TCSI.2007.895369

DOI: 10.1109/TCSI.2007.895369

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