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Implementation of wave-pipelined interconnects in FPGAs

Lookup NU author(s): Dr Terrence Mak, Crescenco D'Alessandro, Professor Alex Yakovlev



Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented. © 2008 IEEE.

Publication metadata

Author(s): Mak T, D'Alessandro C, Sedeole P, Cheung PYK, Yakovlev A, Luk W

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Year of Conference: 2008

Pages: 213-214

Date deposited: 27/05/2010

Publisher: IEEE Computer Society


DOI: 10.1109/NOCS.2008.4492743

Library holdings: Search Newcastle University Library for this item

ISBN: 0769530982