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Lookup NU author(s): Dr Nick Coleman
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We present an implementation of a complete RLS lattice and normalised RLS lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32-bit logarithmic arithmetic. On Virtex XCV2000E6, it takes 22% and 27% of slices respectively and performs at 45 MHz. The cores outperform (4-5 times) the standard DSP solution based on 32-bit floating point TMS320C3x/4x 50 MHz processors. (8 References).
Author(s): Coleman N; Albu F; Kadlec J; Softley C; Matousek R; Hermanek A; Fagan A
Editor(s): Brebner, G., Woods, R.
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Field Programmable Logic and Applications: 11th International Conference (FPL)
Year of Conference: 2001
ISSN: 0302-9743 (print) 1611-3349 (online)
Library holdings: Search Newcastle University Library for this item
Series Title: Lecture Notes in Computer Science