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Post metallization annealing characterization of interface properties of high-K dielectrics stack on silicon carbide

Lookup NU author(s): Ming-Hung Weng, Dr Rajat Mahapatra, Professor Nick Wright, Dr Alton Horsfall


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The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device. © (2009) Trans Tech Publications, Switzerland.

Publication metadata

Author(s): Weng MH, Mahapatra R, Wright NG, Horsfall AB

Editor(s): Suzuki, A., Okumura, H., Kimoto, T., Fuyuki, T., Fukuda, K., Nishizawa, S.

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 12th International Conference on Silicon Carbide and Related Materials (ICSCRM 2007)

Year of Conference: 2009

Pages: 771-774

ISSN: 0255-5476

Publisher: Materials Science Forum: Trans Tech Publications Ltd


DOI: 10.4028/

Library holdings: Search Newcastle University Library for this item

ISBN: 14226375