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A Heuristic Algorithm for Deriving Compact Models of Processor Instruction Sets

Lookup NU author(s): Alessandro De Gennaro, Gladys -, Dr Andrey Mokhov



This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2015.

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Finding a compact formal representation of a processor instruction set is important for easier comprehension by the designer, as well as for synthesis of an efficient hardware implementation of the processor's microcontroller.We present a new heuristic algorithm for deriving compact models of processor instruction sets. The algorithm is based on finding similarities between pairs of instructions and assigning similar opcodes (using a Hamming distance metric) to similar instructions (using a newly introduced instruction similarity metric). We demonstrate that this heuristic produces results with an average overhead, in terms of area, of 7.8\% in comparison to the global optimum on the benchmarks we studied (subsets of instructions of ARM Cortex M0+, Texas Instruments MSP430 and Intel 8051 processors).The algorithm is implemented as an open-source plugin for the Workcraft framework and is validated on a case study of a subset of 61 (out of 68) instructions of ARM Cortex M0+ processor. We compare the presented algorithm against a number of other available implementations.

Publication metadata

Author(s): de Gennaro A, Stankaitis P, Mokhov A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 15th International Conference on Application of Concurrency to System Design

Year of Conference: 2015

Pages: 100-109

Online publication date: 17/12/2015

Acceptance date: 26/03/2015

Date deposited: 10/09/2015

ISSN: 1550-4808

Publisher: IEEE


DOI: 10.1109/ACSD.2015.17

Library holdings: Search Newcastle University Library for this item

Series Title: International Conference on Application of Concurrency to System Design. Proceedings

ISBN: 9781467378826