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Lookup NU author(s): Sami Ramadan, Dr Kelvin Kwa, Dr Peter King, Professor Anthony O'Neill
This is the authors' accepted manuscript of an article that has been published in its final definitive form by IOP Publishing, 2016.
For re-use rights please refer to the publisher's terms and conditions.
The reliable and controllable fabrication of silicon nanowires is achieved, using mature CMOS technology processes. This will enable a low-cost route to integrating novel nanostructures with CMOS logic. The challenge of process repeatability has been overcome by careful study of material properties for processes such as etching and oxidation. By controlling anisotropic wet etching conditions, selection of nitride mask layer properties and sidewall oxidation, a robust process was achieved to realize silicon nanowires with sub 10 nm features. Surface roughness of nanowires was improved by a suitable oxidation step. The influence of process conditions on the shape of the nanowire was studied using TCAD simulation.
Author(s): Ramadan S, Kwa K, King P, O'Neill A
Publication type: Article
Publication status: Published
Journal: Nanotechnology
Year: 2016
Volume: 27
Issue: 42
Online publication date: 08/09/2016
Acceptance date: 11/08/2016
Date deposited: 22/08/2016
ISSN (print): 0957-4484
ISSN (electronic): 1361-6528
Publisher: IOP Publishing
URL: http://dx.doi.org/10.1088/0957-4484/27/42/425302
DOI: 10.1088/0957-4484/27/42/425302
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